Field
Embodiments of the present disclosure generally relate to methods of selective deposition of metal silicides. More specifically, embodiments herein generally relate to metal silicide nanowires in BEOL applications.
Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of components (e.g., transistors, capacitors and resistors) on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit densities. The demand for greater circuit densities necessitates a reduction in the dimensions of the integrated circuit components.
As the dimensions of the integrated circuit components are reduced (e.g., sub-micron dimensions), the materials used to fabricate such components contribute to the electrical performance of such components. As the feature widths decrease, the device current typically remains constant or increases, which results in an increased current density for such features. Higher device densities, faster operating frequencies, and larger die sizes have created a need for a metal with lower resistivity than traditional aluminum to be used in interconnect structures. Copper materials with lower resistivity have been used for decades for its high conductivity. However, as discussed, small size effect may also result in increased resistivity of copper as line widths shrink below around 50 nm and approach the mean free path of electrons in copper (39 nm). The resistivity increase is caused by electron scattering at the surface of the line and at grain boundaries.
Copper (Cu) interconnects have been used as a replacement for Aluminum (Al) for decades. The number of transistors formed on a substrate is reaching a multi-millions range packed in small areas consistent with Moore's law. As the number of transistors increases and the size of transistors decreases, Cu resistivity is exponentially increasing once the metal line dimension approaches or get below the Cu mean free path of 39 nm.
Post Cu era requires new interconnect materials that have low resistivity and narrower mean free path. The mean free path is the average distance traveled by a moving particle (such as an electron, an atom, or a photon) between successive impacts (collisions), which modify its direction or energy or other particle properties. Some metals are already under investigation such as cobalt (Co) interconnect, tungsten (W) Interconnect, and some metal alloys. Silicides, such as Nickel Silicide (Ni—Si) and Cobalt Silicide (CoSi2) interconnects are strong potential candidates given the small mean free path of approximately 5 nm for Ni—Si. Even though Ni—Si resistivity is higher than Cu, the Ni—Si narrow mean free path of approximately 5 nm gives the Ni—Si a strong advantage to replace Cu for advanced future technology nodes of 7 nm and below.
However, current processing methods are not amenable to direct device integration. Most studies involving silicide nanowires have been done with free standing nanowires, as current processing methods can lead to dielectric damage, thermal budget issues, lattice defects and other problems. Regarding thermal budget issues, low resistivity Ni—Si phase formation requires high anneal temperatures of greater than 650 degrees Celsius. Such high anneal temperatures are not suitable in back-end-of-line integration (BEOL), due in part to low-k materials temperature budget limitation (less than about 400 degrees Celsius). Further, controlled growth or selective deposition of nanowire cannot be achieved with existing methods.
Therefore, there is a need for a suitable material for metal interconnection for semiconductor interconnection manufacturing process.